Memory devices are used in a wide variety of applications. Such applications include personal computers, consumer products such as digital cameras, digital video cameras and mobile phones. There exist many different memory devices. The type of memory devices chosen for a specific function depends largely upon what features of these devices are best suited to perform that specific function. For instance, volatile memories, such as dynamic random access memories (DRAMs) must be continually powered in order to retain their contents. However, DRAMs tend to provide greater storage capability and programming option and cycle than non-volatile memories such as read only memories (ROMs). Efforts have been underway to create a commercially viable memory device that is both random access and non-volatile. Ovshinsky et al. disclosed a phase changed memory or chalcogenide random access memory (CRAM), which includes a chalcogenide material or phase change material, in U.S. Pat. No. 5,296,716. The phase change material can be electrically switched between generally amorphous and generally crystalline states. However, the fatigue property is a key issue in CRAM due to high temperature heating. The cell uniformity in products is also a key issue due to the reading method. Since the cell resistance is detected during reading, any non-uniform cell resistance generates an error. A magnetoresistive random access memory (MRAM) device as disclosed by Daughton J. M. in U.S. Pat. No. 4,731,757 and in U.S. Pat. No. 6,021,065 is another type of solid state, non-volatile memory device. A conventional MRAM device includes a column of first electrical wires, referred to as “word lines”, and a row of second electrical wires, referred to as “bit lines”. An array of memory cells located at junctions of the word lines and the bit lines is used to record data signals.
A typical memory cell of a MRAM comprises a magnetoresistive element, wherein the magnetoresistive element comprises a hard magnetic layer, a soft magnetic layer, and a non-magnetic layer sandwiched between the hard magnetic layer and the soft magnetic layer. The hard magnetic layer has its magnetization vector fixed in one direction. The orientation of the fixed magnetization vector does not change under a magnetic field applied thereon. The soft magnetic layer has an alterable magnetization vector under a magnetic field applied thereon, that either points to the same direction, hereinafter “parallel alignment”, or opposite direction, hereinafter “anti-parallel alignment”, of the magnetization vector of the hard magnetic layer. Since the resistances of the magnetoresistive element in the “parallel alignment” status and the “anti-parallel alignment” status are different, the two types of alignment status can be used to record two logical states—the “0”s or “1”s of a data bit.
In a write operation, electric currents pass completely through the word line and the bit line adjacent to a memory cell. When the electric currents reach a certain threshold, the magnetic field generated by the electric currents switches the orientation of the magnetization vector of the soft magnetic layer in the magnetoresistive element. As a result, magnetization of the hard magnetic layer and the soft magnetic layer changes from one type of alignment, e.g. “parallel alignment”, to the other type of alignment, e.g. “anti-parallel alignment”, so that a data bit of a data signal can be recorded in the memory cell.
In order to increase the thermal stability of a memory cell, a Curie point written MRAM has been proposed to improve the MRAM stability, as described in U.S. Pat. No. 6,535,416 to J. M. Daughton et al., and in a paper by R. S. Beech et al. entitled “Curie point written magnetoresistive memory”, J. Appl. Phys. 87, No. 9, pp. 6403-6405, 2000. A Curie point written structure has been disclosed in these structures, where a single pinned layer is used as storage layer. The pinned layer has a higher anisotropy than an unpinned layer that is not pinned by another layer. The use of the pinned layer for information storage provides improved thermal stability, allowing the size of a memory cell to be further reduced before thermal instability becomes a limiting factor.
In order to increase the density of MRAM cells the MRAM structure can be simplified as mentioned in U.S. Pat. No. 6,597,618, U.S. Pat. No. 6,341,084, U.S. Pat. No. 6,317,375 and U.S. Pat. No. 6,259,644.
Most MRAMs use a vertical structure or a current-perpendicular-to-plane (CPP) structure due to their integration with high density in a semiconductor device. The CPP structure may be a magnetic tunnel junction (MTJ) element or a CPP spin-valve element, which are both magnetoresistive elements. Generally, an MTJ element comprises a ferromagnetic free layer such as CoFe, an insulator layer such as AlO, a ferromagnetic pinned layer such as CoFe, and an antiferromagnetic pinning layer. As the size of a memory cell scales down to sub-100 nm, a thin insulator layer less than 1 nm is required to reduce the resistance of the MTJ element. As the insulator layer gets thinner, the resistance uniformity of the MTJ element deteriorates. A typical CPP spin-valve element comprises a ferromagnetic free layer such as CoFe, a metallic space layer such as Cu, a ferromagnetic pinned layer such as CoFe, and an antiferromagnetic pinning layer. As mentioned above, the uniformity of the resistance of the CPP spin-valve element is a key issue. One solution is to detect the magnetization state of the ferromagnetic pinned layer by changing the magnetization state of the ferromagnetic free layer during a read operation. The non-uniformity issue can be overcome by detecting the resistance change. However, as the size of the MTJ element or of the CPP spin-valve element scales down, an increased read power is required to switch the smaller memory cell.